VLSI Schaltungs- und Entwurfstechnik
Titel: | Comparison of Massive-Parallel and FFT based Acquisition Architectures for Multi-Constellation User Receivers |
Autor: | L. Kurz, G. Kappen, T. Coenen, T.G. Noll |
Jahr: | 2010 |
Konferenz / Journal: | Proceedings of the 23rd International Technical Meeting of the Satellite Division of the Institute of Navigation ION GNSS |
Ort: | Portland, Oregon, USA |
Datum: | 21.9.-24.9.2010 |
Seiten: | 2874-2883 |
Kurzfassung: | One of the most important characteristic in performance evaluation and comparison of mass-market receivers is the Time-To-First-Fix (TTFF). Taking a closer look at the architecture of state-of-the-art receivers, it can be observed that mainly two different approaches are followed to decrease TTFF: Either, correlators are massively parallelized or FFT-based techniques for fast convolution are used. For that reason, this contribution addresses a detailed comparison of the two approaches on hardware level for two different platforms: An FPGA-based platform and a 90-nm standard-cell CMOS-technology. The main focus is to provide a detailed cost-benefit analysis that enables a reasonable choice of the acquisition architecture. Costs in this context consider logic-cell count on the FPGA-based platform and silicon chip area on the standard-cell CMOS-technology. Benefit refers to the acquisition speed and accuracy. In detail, the paper is structured as follows: First, the two different approaches are briefly introduced on algorithmic level. While the massive-parallel approach is comparatively straight forward (it can simply be derived from standard tracking channel architectures in common receivers), the FFT-based approach is more complex. Here, the impact of the required FFT-lengths and the word-lengths in the data-path are of major concern. In this context, different requirements in terms of multi-constellation GNSS – in particular GPS, GLONASS, and Galileo E1 – are derived. Afterwards, the hardware setup for both approaches is described. Concerning the FFT-based approach, different setups are considered. Typically, the FFT is computed by executing software code on a standard processor (e.g. DSP, RISC or general purpose processor). In this paper, computations are executed using a special kind of processor, which allows adaptation of the instruction set in accordance to a special application – a so called Application Specific Instruction-Set Processor (ASIP). The processor is described in a special architecture description language (ADL) that allows the processor architecture to be modified in a similar manner like a hardware circuit described in Verilog or VHDL for example. In this paper, successive processor optimizations are demonstrated in order to speed up the FFT computation on the ASIP. Therefore, three different configurations are considered: First, a pure software implementation is demonstrated starting from a RISC-like ASIP architecture. In the following, the ASIP ALU is extended by two different hardware macros. A radix-2 and a radix-4 element are integrated into the ALU in order to increase computational performance. Finally, a setup is analyzed that is completely realized in hardware. In the latter case, the ASIP is used for control purposes only. In the final section of the paper, costs of both acquisition architectures are compared. Considering the massive parallel approach, cost-benefit analysis is comparatively simple since hardware requirements (logic-cell count on the FPGA and chip area for the standard-cell implementation) approximately scale linearly in relation to the acquisition speed. For example, the parallelized acquisition architecture requires nonrecurring resources for the NCOs and code generators of approximately 400 ALUTs plus 35 ALUTs per correlator channel on an Altera Stratix II FPGA. Instantiation of 256 correlator channels on the FPGA for example enables 32 GPS satellites to be acquired after cold start in less than 10 seconds. Evaluating the parallel architecture in a 90-nm CMOS technology, a silicon chip area of approximately 0.012 mm² for the nonrecurring part plus 0.002 mm² per correlator channel have to be taken into account. In contrast, considering the FFT-based approach, costs have to be expressed in terms of processing cycles on the ASIP, resources required for acquisition related instruction set extensions, and additional memory utilization. Investigating the FPGA-based implementation for GPS, the initial software implementation requires about 2 million cycles for a 4092 point FFT based on 16 bit fixed point operands. Using the radix-4 element, the number of processing cycles can be reduced to approximately 0.3 million cycles. Considering costs on the FPGA, the radix-2 element (including a complex multiplier for the multiplication with according twiddle factors) requires about 1250 ALUTs and the radix-4 element about 3600 ALUTs. Results regarding the acquisition speed of the FFT-based solution for GPS are comparable to the massive-parallel approach with 256 correlators, which requires less hardware resources for logic circuitry. However, on FPGA-based platforms memory capacity is often limited. In the context of multi-constellation receivers, the FFT-based approach is only suitable for CDMA-based systems since multiple IFFTs can be computed on one data record transformed into the frequency domain and multiplied by according conjugate complex PRN codes in the frequency domain. In contrast for GLONASS, the presented FFT-based solution turns out to be unsuitable due to the FDMA modulation scheme. In this case, for each satellite and each frequency bin two FFTs (FFT of the input data and IFFT after code multiplication) have to be computed which clearly reduces the acquisition speed. |